[Aboriginal] sh4 target

Rob Landley rob at landley.net
Mon Feb 29 17:44:06 PST 2016

On 02/29/2016 05:08 PM, David Halls wrote:
>     > The sh4 target says it needs a massive cleanup. Was the EXPERT mode fix
>     > taken into the mainline kernel?
>     Yes, in the 4.0 kernel.
>     https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=560b8c0ed45a
>     More recently I've been working with Rich Felker (musl-libc guy), who
>     was just made the new superh co-maintainer.
> I'm not completely up-to-speed on open source / patent free processors. 


> From a few mins reading I came up with this:
> - OpenRISC: from scratch RISC. Not in mainline kernel. Can one buy a
> chip yet?

It's in the mainline kernel since 2011.

> - RISC-V (lowrisc): UCB made it freely available but no chip yet and not
> in mainline kernel.

Not vanilla, but there's a subrepo at https://github.com/riscv/riscv-linux

> - Super-H (sh2 and sh4): Slower than the others (maybe not sh4-64?).
> Kernel has support. sh2 is now patent free, sh4 should be patent free
> this year or next.

SuperH was done by hitachi, which spun off a company called Renesas which
eventually abandoned the stuff they inherited from Hitachi once they
started doing their own stuff.

J-core is a new chip design that implements the superh instruction set.
(Think of it as a clean-room clone.) That became possible with the superh
patents expired.

I haven't benched them against each other, but j-core performs pretty
well. Early versions didn't have d-cache or i-cache, and had an old
dram controller that didn't do burst mode. The current ones have all
that plus SMP and a bunch of DSPs.

Our big initial j-core presentation was covered by


And there's a little bit of wikipediage at:


> I'm taking a wild guess that the above is woefully inaccurate?

Oddly enough, I'm putting together a conference track on this!


It's not officially approved yet, but there have been encouraging
noises. Here's recent-ish correspondence:

On 02/17/2016 08:57 PM, Paul E. McKenney wrote:
> Hello, Rob,
> Great start on the Open Hardware Microconference!


> Have you reached out to the possible interested attendees, and if so, how
> many of them indicated that they were interested in attending?

I pointed a few people at the page, but mostly I didn't want to invite
people to something that didn't exist yet.

We definitely need somebody from https://en.wikipedia.org/wiki/RISC-V
(they're big in this space and Berkeley's reasonably close by). That's
my must-have invite.

I'd also like to ask the http://opencores.org/project,amber guys why
they haven't done armv3 or v4 yet (answer is almost certainly "patents"
but the ensuing discussion should be very interesting).

The architect of OpenRISC (and founder of opencores) seems to live in
Slovenia (https://angel.co/damjan-lampret), but maybe we could get a
skype video thing going for a VHDL vs Verilog discussion if he's not too
deep in the CEO lifestyle these days?

It would also be nice to get somebody from
https://en.wikipedia.org/wiki/LEON but again, Europe. (If the ESA isn't
willing to fly somebody in, we might be able to do skype again, but in
both cases the timezones are against us.)

We'd also like to compare the jcore's build system with
http://bitvis.no/media/19094/Register_Wizard_User_Manual.pdf and
so there's more maintainers to try to track down and invite or skype. (A
panel on hardware build systems would be fun...)

>  (We don't
> need them to have travel approval at this early date -- it is sufficient
> that a fair fraction of them intend to request travel approval.)
> Who else are you looking to attend?

Jeff and Geoff also have lists, and Jen was an early architect of jcore
who probably knows more people. (Those three are mostly in canada
though, again a harder travel sell. We _should_ be able to find silicon
valley people, but I'm told 8 hours down "california's most boring road"
is a bit of a turn-off.)

> 							Thenx, Paul


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